This application claims priority to Korean Patent Application No. 2002-53327 filed on Sep. 4, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device, and more particularly, to a semiconductor memory device having a duty cycle correction circuit correcting the duty cycle of an external clock signal and an interpolation circuit interpolating the clock signal in the semiconductor memory device.
2. Description of the Related Art
The duty cycle of a clock signal is a numerical value representing the ratio of a pulse width with respect to a pulse period of the clock signal. In digital clock applications, it is very important for the duty cycle of a clock signal to be precisely controlled. In synchronous semiconductor memory devices that output data by synchronizing with a clock, when the duty cycle of a clock signal is not precisely controlled distortion of the data can occur. Thus, it is very important to precisely control the duty cycle.
In general, a clock signal with a duty cycle of 50% is mainly used in digital clock applications such as a semiconductor integrated circuit. A duty cycle of 50% means that the high-level and low-level portions of the clock signal are of identical duration. When a clock signal whose duty cycle is not at 50% is input to a duty cycle correction circuit, the duty-cycle correction circuit converts the clock signal whose duty cycle is not at 50% into a clock signal with a duty cycle of 50%.
FIG. 1 shows a duty cycle correction circuit 1000 correcting the duty cycle of an external clock. The duty cycle correction circuit 1000 shown in FIG. 1 includes a delay locked loop 110, an interpolation circuit 120, and an inverting circuit 130.
The delay locked loop 110 receives an external clock CLK_IN and an output signal of the inverting circuit 130, delays the external clock CLK_IN for a predetermined time, and outputs the delayed clock signal. The inverting circuit 130 inverts the output signal of the delay locked loop 110, and outputs the inverted output signal. The interpolation circuit 120 receives the external clock CLK_IN and the output signal CLK_B of the inverting circuit 130, interpolates these signals, and outputs a duty cycle-corrected clock signal CLK_OUT.
FIG. 2 shows internal details of the interpolation circuit 120 from FIG. 1. The interpolation circuit 120 shown in FIG. 2 includes a plurality of inverting circuits 210, 220, and 230. The first and second inverting circuits 210 and 220 are connected to a common output node N1. The output node N1 is an input to the third inverting circuit 230. The first inverting circuit 210 includes a PMOS transistor MP21 and a NMOS transistor MN22, and the second inverting circuit 220 includes a PMOS transistor MP23 and a NMOS transistor MN24. The third inverting circuit 230 receives a signal from the output node N1, and inverts the signal of the output node N1 at a predetermined point in time.
If the clock frequency of the external clock CLK_IN changes, the point in time when the third inverting circuit 230 inverts changes. FIGS. 3A and 3B show the relationships between an input signal and an output signal of an inverting circuit according to the clock frequency of an external clock. In FIG. 3A, the external clock CLK_IN has a low frequency, and in FIG. 3B, the external clock CLK_IN has a high frequency. As shown in FIG. 3A, when the external clock CLK_IN has a low frequency, the slope of the signal at the output node N1 is large. Thus, the point in time when the external clock CLK_IN is inverted changes from a to b to c, and the output signal at the output node N1 changes greatly.
As shown in FIG. 3B, when the external clock CLK_IN has a high frequency, the slope of the signal at the output node N1 is small. Thus, the point in time when the external clock CLK_IN is inverted changes from a to b to c, and the output signal at the output node N1 does not change greatly. However, when the external clock CLK_IN has a high frequency, since a drop in the speed of the clock signal is slow, the clock signal is not completely swung from a low voltage to a high voltage.